1. Field of the Invention
The present invention relates generally to an inspection and analyzing apparatus for a semiconductor integrated circuit, and a method therefor. More particularly, the invention relates to an inspection and analyzing system for a semiconductor integrated circuit that includes circuit elements arranged on a semiconductor.
2. Description of the Related Art
In inspection and analysis of an integrated circuit that has been constructed by arranging circuit elements on a semiconductor, a distribution of faulty circuit elements can be visually perceived by plotting the positions of faulty circuit circuit elements.
For example, a circuit for driving the circuit element group is divided into blocks. If all circuit elements involved in each block fail, there has been a block failure. On the other hand, if all of the faulty circuit elements having a common wiring, there has been a wiring failure. Furthermore, when a failure occurs in a single circuit element, a one bit failure has occured. On the other hand, when adjacent circuit elements fail in a group, there has been a group failure.
Such an inspection analysis and analyzing method is know as bit map analyzing and is effetive for failure analysis of semiconductor integrated circuit device, such as LSI memories and the like. However, when the number of the circuit elements exceeds about a million manual analysis of all of the causes of faulty circuit elements is difficult.
On the other hand, Japanese Unexamined Patent Publication No. Showa 61-23327 discloses a technology in which a portion where a failure has occurred is detected to find an error in a fabrication process on the basis of a distribution of kind of the failure. Namely, instead of testing a fabrication line, a faulty device is inspected to detect where the failures occurred.
For example, in a storage device, when adjacent two capacitors have a short portion through a substrate due to absence of a necessary field oxide, failure is indicated for two bits, i.e. each bit of a corresponding column and row of a memory array. Then, on the basis of a failure pattern of an address selection (ADSEL) algorithm, the faulty portion can be located.
Then, a distribution of kinds of defect in the array of of the storage device and the distribution of particular date are compared data in the past to evaluate whether time, temperature and material has not be provided according to a specification in a particular process of the fabricating operation. Then, the particular faulty mechanism is replaced.
In the technology disclosed in Japanese Unexamined Patent Publication No. Showa 61-23327, it has not been possible to distinguish between a defect caused by a design and detect caused by a fabrication process. Therefore, in the semiconductor integrated circuit, in case of distribution of the faulty elements which is visually perceived to be irregular, prediction of a cause of failure based on the shape of the distribution becomes difficult.
The present invention has been worked out in order to solve the problem in the prior art. Therefore, it is an object of the present invention to provide and inspection and analyzing apparatus of a semiconductor integrated circuit, and a method therefor, which can qualitatively and quantitatively distinguish a cause of a failure between a defect due to design and a defect due to other causes by analyzing the kind and frequency of a divisor of an interval between respective faulty elements.
According to one aspect of the present invention, an inspection and analyzing apparatus of a semiconductor integrated circuit comprises:
interval calculating means for calculating an interval |xcex94x| in an X-direction, an interval |xcex94y| in a Y-direction and an interval |xcex94xy| derived by multiplying the X-coordinate and the Y-direction between faulty elements with each other in an XY orthogonal coordinate system representative of a positional relationship of circuit element groups arranged on a semiconductor element;
divisor calculating means for calculating divisors for respective values of the intervals |xcex94x|, |xcex94y| and |xcex94xy| and further calculating a number xcexa3m of each divisor; and
judgment means for evaluating a relationship between a distribution of the faulty elements and a design standard for the kind and number xcexa3m of the divisors for the circuit being tested. Then, the judgment means may derive respective functions of R(x, f)=xcexa3m/Nx, R(y, f)=xcexa3m/Ny, R(xy, f)=xcexa3m/Nxy when total numbers of respective values of the intervals |xcex94x|, |xcex94y| and |xcex94xy| are Nx, Ny and Nxy, respectively, and evaluate a relationship between a distribution of the faulty element and a design standard for a distribution condition of the values of the divisor f.
Also, the judgment means may further derive functions R(x, f)*f, R(y, f)*f and R(xy, f)*f by multiplying respective ones of the functions by f, and evaluating of a relationship between a distribution of the faulty element and a design standard for a distribution condition of the values of the divisor f.
The judgment means may indicate that the faulty elements are in irregular positional relationship when the individual values of each of the functions corresponding to a prime number in the divisor f is greater than that of other values of the divisor. When irregular positional relationship are found, a fabrication is probably at fault.
The judgment means may indicate that the faulty element has a relationship with the design standard when respective individual values of respective functions corresponding to an even number among the the divisors f is majority in comparison with those of other divisors.
According to another aspect of the present invention, an inspection and analyzing method of a semiconductor integrated circuit comprises:
a step of exhaustively calculating an interval |xcex94x| in an X-direction, an interval |xcex94y| in a Y-direction and an interval |xcex94xy| derived by multiplying the X-coordinate and the Y-direction between faulty elements with each other in an XY orthogonal coordinate system representative of positional relationship of circuit element groups arranged on a semiconductor;
a step of calculating divisors for respective values of the intervals |xcex94x|, |xcex94y| and |xcex94xy| and further calculating number xcexa3m of each divisor; and
a judgment step of evaluating a of relationship between a distribution of the faulty element and a design standard depending upon the kind and number xcexa3m of the divisors.
Then, the judgment step includes a step of deriving respective functions of R(x, f)=xcexa3m/Nx, R(y, f) xcexa3m/Ny, R(xy, f)=xcexa3m/Nxy when total numbers of respective values of the intervals |xcex94x|, |xcex94y| and |xcex94xy| are Nx, Ny and Nxy, respectively, and a step of indicating a relationship between a distribution of the faulty element and a design standard depending upon a distribution condition of respective values in relation to the divisor f, with reference to the values relative of each individual f of each of the functions.
Also, the judgment step may further comprise a step of deriving functions R(x, f)*f, R(y, f)*f and R(xy, f) *f by multiplying respective of the functions by f, and a step of evaluating a relationship between a distribution of the faulty elements and a design standard depending upon a distribution condition of respective values of the divisor f.
In the operation of the present invention, the inspection and analyzing apparatus and method of a semiconductor integrated circuit exhaustively calculates an interval |xcex94x| in an X-direction, an interval |xcex94y| in a Y-direction and an interval |xcex94xy| derived by multiplying the X-coordinate and the Y-coordinate between faulty elements with each other in an XY orthogonal coordinate system representative of positional relationship of circuit element groups arranged on a semiconductor, calculates divisors for respective values of the intervals |xcex94x|, |xcex94y| and |xcex94xy| and further calculates a number xcexa3m of each divisor, and evalutes a relationship between a distribution of the faulty elements and a design standard depending upon kind and number xcexa3m of the divisors.
Most LSI memories are designed to have a circuit design and layout according to a rule of exponentiation of 2 for making one electrode in common with two memory elements, for driving wiring per a unit of two wires or four wires, for arranging circuit driving four wires symmetrically (per 8 wires), and for driving sixteen wires by one driving circuit. Namely, since the design rule of the memory does not include prime numbers of 3, 5, 7, 9, 11, 13, 17, 19 . . . , the distribution of the faulty elements includes prime numbers other than two in the divisors of the interval of the faulty elements, it can be predicted that failure is caused by something other than circuit design or layout design.
Accordingly, by the present invention, when the distribution of the divisors of the intervals between the faulty elements includes the prime number having no relation with a design rule for the circuit and a relationship with with the yield of the fabrication process for the semiconductor integrated circuit is checked, effective means for detecting and analyzing the cause of the failures can be provided.